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What is UCIe, the new standard that promises to change the semiconductor industry

Intel, TSMC, Samsung, ARM and Qualcomm, among others, joined forces to create a consortium to standardize the chiplet ecosystem. Next, we will tell you what the Universal Chiplet Interconnect Express (UCIe) is about and what is sought with it.

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The most important companies in the field of semiconductors have joined forces to create a consortium that aims to standardize the chiplet ecosystem. We are talking about Intel, ARM, Qualcomm, TSMC and Samsung, among others; they will join forces in search of reducing production costs and universalizing chiplet interconnection. For this , they propose the Universal Chiplet Interconnect Express (UCIe) , as the answer for the design and manufacture of the SoCs of the future.

The project is as interesting as it is technical; therefore we will try to explain its main points in the most understandable way possible. It is important to note that behind this initiative are not only the world’s leading chip designers, but also corporations such as Microsoft, Meta (Facebook) and Google, as providers of cloud services.

Through UCIe, its promoters seek to standardize the interconnection between chiplets based on an open source design . This seeks to “break” the parameters that currently exist, where solutions are proprietary and that prevents direct compatibility between chiplets designed by different companies.

What are chiplets, after all?

The term “chiplet” is not necessarily new, although only in the last five years has it been heard more frequently. Chiplets are the alternative to monolithic architecture for processor design and manufacturing. We are talking about the use of independent components that are grouped together to form a larger chip.

This brings with it several benefits. In the first instance, by dealing with smaller chips it is possible to lower production costs; in turn, as it is a modular assembly, if a problem occurs with one of the parts, it can be repaired. Thus, if there is a failure in the memory but not in the cores, the processor should not be discarded completely (as it happens in the monolithic design) but only the chiplet that is presenting problems.

However, chiplets are not without some drawbacks. Historically, its most problematic aspect is latency , which occurs because the various circuits are not in direct contact. This means that the data takes longer to travel between the chiplets. It is worth noting, however, that the UCIe promises to address this weakness.

AMD and Intel are the companies that have most pushed the adoption of chiplets in the design of their respective hardware in recent years. A bet that began at the end of 2018 with the introduction of the 7 nanometer AMD Zen 2 architecture and the problematic 10nm Intel Sunny Cove processors.

The UCIe standard sets out to change the SoCs of the future

One of the analogies that has been seen the most these days to explain how this proposal will work is that of LEGO blocks. The consortium behind Universal Chiplet Interconnect Express proposes that the new standard allow SoC manufacturers to choose which components to use, no matter who makes them . To do this, the UCIe 1.0 specification takes advantage of two protocols that are well established in the industry, such as CXL and PCIe . In addition, it promises cost-effective performance and energy efficiency.

If we look for a super simplified comparison of what this new standard will bring to the semiconductor industry, we could say that under UCIe manufacturers will be able to incorporate different chiplets into their designs with the same ease that today we can install a solid state drive via NVMe , or a graphics card via PCIe.

UCIe is the result of industry leaders working together to develop a common standard that allows multiple chiplets from different sources to interoperate seamlessly. While UCIe sponsors cover a broad intersection of cloud services, semiconductor manufacturing, OSATs, IP providers, and chip designers, the consortium is open to all. UCIe is poised to be the ubiquitous interconnect that powers a thriving open ecosystem of chiplets.

Whitepaper del Universal Chiplet Interconnect Express

If you are looking for more technical information on how standardization is intended to be implemented for the chiplet ecosystem, Tom’s Hardware has published a very interesting article. It explores what the performance goals are, as well as the implementation of the physical and protocol layers, among other issues.

A vision that requires a lot of work

That the major exponents of the semiconductor industry (both designers and foundries) are on board the Universal Chiplet Interconnect Express, is very promising. In any case, there is still a long way to go to see the results of this initiative reflected.

And while this consortium is taking its first steps, the expectation is that more companies will join. UCIe promoters already intend to work on defining several important points for the future of the standard; among many, the form factor of the chiplets, their management, security optimization , and other “essential protocols”.

“The fact that it is an open standard with a plug-and-play model, inspired by several successful standards, and launched by the right group of industry leaders will ensure its widespread adoption. We anticipate that the next generation of innovations will happen at the of the chiplet, which will allow a set of chiplets to offer different capabilities for the customer to choose the one that best suits their application requirements,” they said .

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